1. Field
Exemplary embodiments of the present invention relate to a non-volatile memory device and a method for fabricating the same, and more particularly, to a non-volatile memory device with a three-dimensional structure, where a plurality of memory cells are stacked along a channel protruding perpendicularly from a substrate, and a method for fabricating the same.
2. Description of the Related Art
A non-volatile memory device is a memory device where stored data is retained even when a power supply is cut off. An example of a non-volatile memory device is a flash memory.
Meanwhile, as an increase in the degree of integration of a memory device with a two-dimensional structure, wherein memory cells are formed as a single layer on a silicon substrate, approaches a limit, a proposed configuration is a non-volatile memory device with a three-dimensional structure, wherein a plurality of memory cells are stacked along a channel protruding perpendicularly from a silicon substrate.
The configuration of a conventional non-volatile memory device with a three-dimensional structure will be described in more detail below.
A lower selection transistor, memory cells with a multilayer structure, and an upper selection transistor are sequentially stacked over a silicon substrate to form a non-volatile memory device with a three dimensional structure. The lower selection transistor is formed with a pillar-shaped lower channel connected to a source region formed in the silicon substrate, a lower selection gate electrode arranged on a sidewall of the lower channel, and a gate dielectric layer interposed between the lower channel and the lower selection gate. The memory cells with a multilayer structure are formed with a pillar-shaped cell channel connected to the lower channel, cell gate electrodes arranged on a sidewall of the cell channel in a multilayer structure, and a memory layer interposed between the cell gate electrodes and the cell channel. The upper selection transistor is formed with a pillar-shaped upper channel connected to the cell channel, an upper selection gate electrode arranged on a sidewall of the upper channel, and a gate dielectric layer interposed between the upper channel and the upper selection gate.
More specifically, the lower channel, the cell channel, and the upper channel are connected to one another and protrude perpendicularly from the substrate. Also, the lower selection gate electrode, the cell gate electrodes, and the upper selection gate electrode are stacked in a multilayer structure along the channels with insulation layers interposed between the electrodes to isolate the electrodes from one another.
To increase the integration degree of conventional non-volatile memory devices by using the above-described method, a number of memory cells may be stacked. However, in increasing the number of stacked memory cells, physical limits are being reached with available fabrication processes.
Furthermore, according to the conventional art, since a process of forming the lower selection transistor, a process of forming the memory cell with a multilayer structure, and a process of forming the upper selection transistor are separately performed in a sequential manner, the fabrication process may be complicated.